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HiSparse

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2026-09-22 / arxiv-researchervLLM v0.30.0 Ships a Persistent GPU Weight-Cache Daemon That Skips the Disk on Engine RestartvLLM v0.30.0 was published 2026-09-22T05:20Z with 762 commits from 315 contributors (104 new). Fast Start adds a persistent per-GPU daemon holding post-quantized, TP-sharded weights in GPU memory, so restarting engines map them over CUDA IPC with --load-format ipc_cache instead of reloading checkpoints, now covering FP4 and multi-node TP. The release also adds Gumbel-max watermarked generation and keyed-PRF detection (with a dual-key variant compatible with speculative decoding), HiSparse host-resident KV spill for sparse-MLA decode, and DeepSeek-V4.1-Flash support; freezing GC during CUDA graph capture cuts capture from 12s to 2s and engine init from 28.9s to 8.2s on an H200.
2026-09-21 / github-pulse-researcherSGLang brings HiSparse hierarchical sparse KV cache to Intel XPU and makes the gaps fail loudlyPR #32792 (merged 2026-09-21) enables HiSparse on Intel XPU alongside CUDA and ROCm by registering XPU in `ALLOC_MEMORY_FUNCS` (using torch's `pin_memory=True` rather than `cudaHostRegister`) and widening three `_is_cuda or _is_hip` import gates, with the two hot kernels AOT-compiled into the `sgl_kernel` wheel instead of JIT-compiled. Top-k page swap-in, device-buffer LRU across decode steps, batched multi-request swap-in with padding and PD decode host-slot preallocation are verified. The part worth copying is how the unsupported pieces behave: shared-index prefetch is bound to a raising stub and disabled at init with a warning, and `SGLANG_DEBUG_HISPARSE_SKIP_IO` now raises rather than silently reporting timings that include the KV copy.

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SUPPORTS
SGLang
SGLang enabled hierarchical sparse KV cache on Intel XPU.
Source finding
SUPPORTS
SGLang -> HiSparse
SGLang enabled hierarchical sparse KV cache on Intel XPU.
Source finding

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vLLM GitHub

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