Dwarkesh Patel: Reiner Pope Builds Chip Design From Logic Gates to TPUs — Full-Stack Hardware Explainer

Dwarkesh Podcast·medium signal

MatX CEO and former Google TPU architect Reiner Pope walks through chip design from first principles in a blackboard-style Dwarkesh Podcast lecture, covering multiply-accumulate circuits from logic gates, systolic arrays, pipeline registers, FPGAs vs ASICs, cache vs scratchpad memory, and why CPU cores are much larger than GPU cores. Pope is one of a handful of people who understand the full AI stack from transistor to transformer.