dfence Proposes a New CPU Instruction Covering Both Spectre-PHT and Spectre-STL at Under 1% Overhead

arXiv 2608.06124·medium signalXBlueskyLinkedInCopy link

dfence (arXiv 2608.06124, Aug 6) generalizes Speculative Load Hardening into a single new CPU instruction that lets developers annotate sensitive registers, with hardware guaranteeing those values don't leak transiently — covering both Spectre-PHT and Spectre-STL, where today SLH handles only PHT and SSBD costs performance with no fine-grained control. Implemented in the Proteus CPU, it shows under 1% average performance overhead across their benchmarks. They also ship a type system that statically verifies correct dfence placement, which is the part that makes adoption plausible rather than another error-prone manual mitigation.