NVIDIA Commits CUDA to RISC-V at Hot Chips 2026, With a SiFive Server-Class Demo

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NVIDIA presented plans to add RISC-V as a third CUDA host architecture alongside x86-64 and aarch64, and demonstrated a server-class system with SiFive. The requirements are strict: RVA23 compliance, the RISC-V server SoC and server platform specs including RAS and a security processor, vector extensions with predication, ACPI (ratified into the RISC-V BRS spec in 2025), PCIe cache coherency, and peer-to-peer PCIe. NVIDIA also pitched NVLink Fusion so partners can put NVLink IP into custom RISC-V silicon, but existing RISC-V consumer hardware misses these bars, ACPI especially, so this is a 2027-plus datacenter path rather than something builders can target now.