Jalapeño Is a Reticle-Sized ASIC Built in a Nine-Month Cycle, With Celestica Doing Rack Integration

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The companion OpenAI/Broadcom announcement details Jalapeño as a massive reticle-sized ASIC taken from design to silicon in roughly nine months, with Broadcom supplying the physical implementation plus networking and connectivity, and Celestica handling board, rack and system integration. The design specifically targets prefill and inter-chip communication phases, which OpenAI names as the dominant bottlenecks in serving. The nine-month cycle is the number to watch: it implies a custom-silicon cadence closer to a product release than a traditional chip program.