Samsung's LPDDR5X-PIM Runs 614 GB/s Internally Against 76.8 GB/s Over the Bus, at 1.2 TOPS Per Chip

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At Hot Chips 2026 Samsung presented LPDDR5X-PIM, which puts multiply-accumulate units inside the DRAM banks while staying compatible with standard memory controllers. Internal bandwidth across all 16 banks reaches 614 GB/s versus 76.8 GB/s maximum over the normal interface, with 1.2 TOPS of INT8/FP8 per chip doubling to 2.4 TOPS at 4-bit weights, which is where memory-bound local LLM decode would benefit. The software problems are real: PIM memory must be marked uncacheable, prefetching breaks, and PIM modes redefine DRAM access commands so you cannot mix PIM and normal traffic, which makes multitasking hard.