Show HN: Auto-Architecture — Karpathy's Loop Pointed at a CPU, Achieves +92% Performance — 155 Points on HN
GitHub / Hacker News·high signal
FeSens applied Karpathy's autonomous experiment loop to CPU architecture design, starting with a textbook 5-stage RV32IM core in SystemVerilog. The AI-driven evolutionary search achieved +92% over locked baseline and +56% over VexRiscv on CoreMark, with 40% fewer LUTs. Gains compound: ~13% architectural efficiency plus higher Fmax (199 vs 144 MHz) — a smaller, simpler design the synthesizer also clocks faster. 155 points, 32 comments.