Microsoft's Maia 200 paper claims 10,145 Tflop/s FP4

Microsoft laid out specs for its Maia 200 inference chip in the Maia 200 paper, posted to arXiv. It claims 10,145 Tflop/s of FP4 throughput inside a 750-watt power budget. The company says the chip targets inference workloads specifically, for cost and energy reasons rather than raw peak performance.

The architecture is what Microsoft calls a Software Defined Locally Accessed Dataflow Architecture. Dataflow engines route data directly between specialized memory pools, so computation follows the data movement instead of organizing around threads. The chip pairs that design with 7 TB/s of HBM bandwidth.

FP8 throughput reaches 5,072 Tflop/s, about half the FP4 number, which tracks with what doubling precision typically costs in speed.

These are Microsoft's own figures. No outside lab has benchmarked Maia 200, so the throughput claims stand as vendor-reported until someone runs it independently. The 750-watt ceiling also matches Jalapeño, another inference chip built to the same power limit.