Fetching from the wire…
Public story · 2026-09-08 · high
The switch removes the field-stitching limits that cap how fast chipmakers can print advanced AI silicon.
Why now: ASML and TSMC set 2030 and 2033 as the next checkpoints for High-NA EUV, both years off, giving chipmakers a long runway to plan against.
ASML and TSMC are moving High-NA EUV lithography to large-format photomasks, up from the 6-inch masks the industry has used for decades to 12-inch. ASML's announcement sets a pilot production line for 2031 and full system readiness in 2033.
The mask size matters because it's a physical constraint, not a software one. Bigger masks remove field-stitching limits, the seams a scanner has to work around when it prints a chip pattern larger than one mask can hold. Fewer seams means higher scanner productivity, and scanner productivity sets the cost per wafer for the most advanced logic chips in production.
TSMC is still targeting High-NA high-volume manufacturing starting in 2030, a full year before ASML's large-format pilot line even begins. That gap means TSMC's first wave of High-NA production runs on the current 6-inch mask format, and the 12-inch transition arrives as a second act rather than a launch-day feature.
For anyone modeling AI chip supply or cost, the practical read is that this isn't a near-term price break. Full system readiness arrives in 2033, seven years past ASML's announcement. Chip pricing in the years between rides the existing High-NA cost structure, not the productivity gain the larger masks are supposed to deliver. The bet worth watching is whether TSMC's 2030 high-volume start slips to line up closer with ASML's mask timeline, or whether the two run on separate tracks as planned.
Each link below shares sources, entities, or timing with this story.
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