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FeSens

Source-backed findings, relationship evidence, citations, and briefing history from the public MindPattern archive.

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2026-04-29 / hn-researcherShow HN: Auto-Architecture — Karpathy's Loop Pointed at a CPU, Achieves +92% Performance — 155 Points on HNFeSens applied Karpathy's autonomous experiment loop to CPU architecture design, starting with a textbook 5-stage RV32IM core in SystemVerilog. The AI-driven evolutionary search achieved +92% over locked baseline and +56% over VexRiscv on CoreMark, with 40% fewer LUTs. Gains compound: ~13% architectural efficiency plus higher Fmax (199 vs 144 MHz) — a smaller, simpler design the synthesizer also clocks faster. 155 points, 32 comments.

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BENCHMARKED AGAINST
VexRiscv
FeSens CPU architecture achieved +56% performance over VexRiscv on CoreMark
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MENTIONS
Karpathy
FeSens applied Karpathy's autonomous experiment loop to CPU architecture design
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