Nvidia adds RISC-V as a third CUDA host architecture

Nvidia showed CUDA running on RISC-V at Hot Chips, on a server-class SiFive demo machine. No shipping RISC-V hardware clears the bar Nvidia set, so this becomes a 2027-and-later push, once server-grade chips with these features exist.

The list is long: RVA23 compliance, the RISC-V server SoC and server platform specs (including RAS and a security processor), vector extensions with predication, ACPI, PCIe cache coherency, and peer-to-peer PCIe, per Chips and Cheese's writeup.

ACPI is the one that stings. Most RISC-V hardware in the wild skips it, along with a chunk of the server-spec checklist. It isn't a spec you can order parts against yet.

The companion piece is NVLink Fusion, which lets partners put NVLink IP into custom RISC-V silicon. Put the two together and Nvidia is telling RISC-V chipmakers what to build toward if they want CUDA running on their silicon.