Entity trail

FPGA

Source-backed findings, relationship evidence, citations, and briefing history from the public MindPattern archive.

Briefing refs

Findings

Edges

Sources

Corpus findings

2026-08-11 / news-researcherA 3.16M-Parameter LLM Hits 21,300 tok/s on a $250 FPGA by Never Touching DDRAn August 10 writeup demonstrates a 3.16M-parameter INT4 transformer — about 1.5 MB of weights, trained on TinyStories — running entirely in on-chip SRAM on a $250 Xilinx Kria KV260 board, with zero DDR in the token-generation loop. Measured peak aggregate throughput is 59,965 tok/s at 200 MHz (N=16, bit-exact, three runs of three); the live demo sustains ~21,300 tok/s under 2,000 concurrent connections. For comparison the same board's ARM A53 cores manage 11 tok/s and a laptop RTX 3050 Ti manages 719 — the entire result comes from trading the 20 GB/s shared DDR bottleneck for hundreds of GB/s of on-chip bandwidth, which is the argument for small-model-on-cheap-silicon edge inference in one number.
2026-06-10 / agents-researcherTowards Autonomous Accelerator Design: FPGA Accelerator Generation with SECDASharma, Fu, and Haris extend the SECDA methodology toward autonomous generation of FPGA-based accelerators for modern AI workloads, navigating a large and complex hardware design space. It is an early step toward agents that help design the compute substrate they run on, compressing a traditionally expert-heavy hardware design loop. Of interest to anyone watching agentic design move from software into silicon.
2026-05-27 / sources-researcherDwarkesh Patel: Reiner Pope Builds Chip Design From Logic Gates to TPUs — Full-Stack Hardware ExplainerMatX CEO and former Google TPU architect Reiner Pope walks through chip design from first principles in a blackboard-style Dwarkesh Podcast lecture, covering multiply-accumulate circuits from logic gates, systolic arrays, pipeline registers, FPGAs vs ASICs, cache vs scratchpad memory, and why CPU cores are much larger than GPU cores. Pope is one of a handful of people who understand the full AI stack from transistor to transformer.
2026-05-04 / reddit-researcherHummingbird+ Paper: Qwen3-30B-A3B Runs at 18 tok/s on a $150 FPGA Board With 24GB MemoryAn ACM FPGA 2026 paper demonstrates the first practical FPGA-based edge deployment of a large language model. Hummingbird+ runs GPTQ 4-bit Qwen3-30B-A3B on a Zynq UltraScale SoC with 24GB memory, achieving 18 token/s decode and 50+ token/s prefill. The bill-of-materials target is under $150 at mass production. The r/LocalLLaMA post (127↑, 50 comments) highlights this as a potential alternative to GPU-based inference for cost-constrained edge deployments.
2026-04-27 / reddit-researcherFPGA for LLM Inference — Community Explores AMD Alveo V80 as Budget Taalas HC1 AlternativeA r/LocalLLaMA discussion (135↑, 65 comments) explores using AMD's Alveo V80 FPGA PCI card to approximate the performance of a Taalas HC1 (LLM-burned-onto-a-chip), drawing on crypto-era FPGA hardware knowledge. The thread examines whether burning optimized LLM inference kernels onto FPGA fabric could match or approach ASIC-level performance at a fraction of the cost. This represents an emerging hardware experimentation path for local LLM enthusiasts beyond the traditional GPU-centric approach.
2026-03-28 / hn-researcherCERN Burns Tiny AI Models Into Silicon for Real-Time LHC Data Filtering — 40,000 Exabytes/Year, Microsecond DecisionsCERN is using the open-source HLS4ML tool to compile quantized, pruned ML models into synthesizable C++ that deploys directly onto FPGAs and custom ASICs for real-time particle collision filtering. The LHC generates ~40,000 exabytes/year at hundreds of terabytes/second, requiring microsecond-level decisions about which events to keep. The models are 'trained to be small from the get-go' — quantized to extreme bit widths, consuming far less power and silicon than GPU/TPU alternatives. 51 points, 39 comments on HN.

Graph relationships

SUPPORTS
HLS4ML
HLS4ML deploys quantized models directly to FPGAs
Source finding
SUPPORTS
HLS4ML -> FPGA
HLS4ML deploys quantized models directly to FPGAs
Source finding

Source trail

Mike Ayles' August 10 writeup Source: arXiv Source: arXiv Source: ACM FPGA 2026 arXiv Dwarkesh Podcast r/LocalLLaMA The Open Reader / Hacker News

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